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rohm limited corporation technical note for lcd panel backlight white led driver ic under development BD8108FM outline BD8108FM is a white led driver of high-withstand-voltage (36v). step-up dc/dc converter and constant current output 4ch are built-in in 1chip. the brightness can be controlled by either pwm or vdac. features 1) input voltage range 4.5 ? 30v 2) built-in step-up dc/dc controller 3) built-in current driver 4ch (150ma max.) for led drive 4) compatible with pwm light-modulating 0.38 ? 99.5% 5) built-in protective functions (uvlo, ovp, tsd, ocp) 6) built-in abnormal-status- detecting function (open/short) 7) hsop-m28 package application car navigation backlight and small & medium-sized lcd panel etc. absolute maximum ratings (ta=25 ? ) item symbol rating unit power supply voltage (pin : 1) v cc 36 v load switch output voltage (pin : 2) v loadsw 36 v led output voltage(pi n : 12,14,15,17) v led 36 v fail output voltage (pin : 3,20) v ol 7 v input voltage (pin : 5,6,10,11,24) v in -0.3 ? 7 < v cc v vdac input voltage (pin : 8) v dac -0.3 ? 7 < v cc v allowable loss pd 2.20 t 1 w junction temperature tjmax 150 ? operating temperature range topr -40 ? +95 ? storage temperature range tstg -55 ? +150 ? led maximum output current (pin : 12,14,15,17) i led 150 tt ma t 1 it is mounted on a glass epoxy board of 70mm70mm1.6mm. and the allowable loss is reduced at a rate of 17.6mw/ ? at the time of over 25 ? t 2 dispersion between columns of led maximum output current and v f is correlated. please refer to data on a separate sheet. t 3 amount of the current per 1ch. operating condition (ta=25 ? ) item symbol target value unit power supply voltage (pin : 1) v cc 4.5 ? 30 v oscillating frequency range f osc 50 ? 550 khz external synchronization frequency range tt (pin : 6) f sync fosc ? 550 khz external synchronization pulse duty range (pin : 6) f sduty 40 ? 60 % t 4 please connect sync to gnd when exter nal synchronization frequency is not used. t 5 do not do such things as switching over to internal o scillating frequency while external synchronization frequency is used. 2007.jan. rev. 0.14
2/16 electric characteristic (unless otherwise specified, vcc=12v ta=25 ? ) target value symbol minimum standard maximum unit condition circuit current i cc 2.5 6 10 ma en=2v, sync=vreg, rt=open pwm=open, iset=open, c in =1f standby current i st - 0 2 a en=low [vreg part (vreg)] reference voltage v reg 4.5 5 5.5 v i reg =-10ma, c reg =1f [sw part (swout,cs)] swout upper on resistance r onh 0.05 3 7 ? i on =-10ma swout lower on resistance r onl 0.05 2 5 ? i on =10ma overcurrent protection operating voltage v dcs 0.3 0.4 0.5 v v cs =sweep up [error ? amplifier (comp,ss)] led control voltage v led 0.7 0.8 0.9 v comp sink current i skcp 40 100 200 a v led =2v, vcomp=1v comp source current i sccp -200 -100 -40 a v led =0v, vcomp=1v ss charging current i ss -14 -10 -6 a v ss 1 1.0v ss maximum voltage v mxss 2.0 2.5 3.0 v en 1 high ss standby current i stss - 0 2 a en 1 low [oscillator part (rt,swout)] oscillating frequency f osc 250 300 350 khz r t =100k ? [ovp part (ovp)] overvoltage-detecting reference voltage v dovp 1.86 2.0 2.14 v v ovp =sweep up ovp hysteresis width v dohs 0.35 0.45 0.55 v v ovp =sweep down [uvlo part (vreg)] reduced-voltage detecting reference voltage v duvlo 2.5 2.8 3.1 v v reg =sweep down uvlo hysteresis width v duhs 50 100 200 mv v reg =sweep up [load switch part open drain (loadsw)] load switch low voltage v ldl 0.05 0.15 0.3 v i load =10ma [led output part (led1-4,iset,pwm,vdac,ovp)] led current relative dispersion width i led1 - 3 - % i led =50ma led current absolute dispersion width i led2 - 5 - % i led =50ma iset voltage v iset 1.92 2.0 2.08 v pwm light modulation duty 0.38 - 99.5 % f pwm =150hz, i led =50ma t pwm frequency f pwm 0 - 20 khz duty=50% | i led =50ma t vdac gain g vdac 20 25 30 ma/v v dac =0 ? 2v, i led =50ma t open detecting voltage 1 v dop1 0.05 0.15 0.3 v v led = sweep down, v ovp ? v dop2 , v ss ? v mxss open detecting voltage 2 v dop2 1.56 1.7 1.84 v v ovp = sweep up, v led ? v dop1 , v ss v mxss short detecting voltage v dsht 4.0 4.5 5.0 v v led = sweep up, , v ss ? v mxss [logic input en,sync,pwm,leden1,leden2 ] input high voltage v inh 3.0 - 5.5 v input low voltage v inl gnd - 0.8 v input inflowing current i in 18 35 53 a v in =5v (sync,pwm,leden1,leden2) input inflowing current i en 13 25 38 a v en =5v (en) [fail output open drain (fail1,fail2)] fail low voltage v fll 0.05 0.1 0.2 v i ol =1 < a ? there is no radiation-proof design in this product. t 1 0%,100% input is possible t 2 i led =v dac r iset 3300 t 3 i led =v iset r iset 3300, v dac ? v iset
3/16 reference data (unless otherwise specified, ta=25 ? ) d 0.0 2.0 4.0 6.0 8.0 0 6 12 18 24 30 36 vcc [v] icc [ma] 30 35 40 45 50 -40 -15 10 35 60 85 ta [ ? ] iled [ma] fig.6 efficiency 20 40 60 80 100 120 40 140 240 340 440 540 total_io [ma] efficiency [%] 0.70 0.75 0.80 0.85 0.90 -40 -15 10 35 60 85 ta [ ? ] vled [v] 0.30 0.35 0.40 0.45 0.50 -40 -15 10 35 60 85 ta [ ? ] vcs [v] 30 35 40 45 50 -40 -15 10 35 60 85 ta [ ? ] iled [ma] 0 1 2 3 4 5 6 0 40 80 120 160 i vreg [ma] vreg [v] 4.5 4.7 4.9 5.1 5.3 5.5 -40 -15 10 35 60 85 ta [ ? ] vreg [v] fig.1 vreg temperature characteristic fig.4 iled?s dependence on vled fig.5 iled temperature characteristic fig.7 i cc -v cc fig.2 vreg current capacity fig.8 overcurrent detecting voltage temperature characteristic fig.9 vled temperature characteristic fig.3 osc temperature characteristic 200 240 280 320 360 400 -40 -15 10 35 60 85 ta [ ? ] osc frequency [khz] 0 2 4 6 8 10 012345 ven [v] 73&(<7> 0 10 20 30 40 50 60 00.511.52 vdac [v] iled [ma] 0 2 4 6 8 10 012345 v pwm [v] vreg [v] fig.10 en threshold voltage fig.11 pwm threshold voltage fig.12 vdac gain vcc=12v vcc=12v vcc=12v vcc=12v vcc=10v vcc=6v vcc=8v ta =2 5 ? t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d.
4/16 block diagram fig.13 pin layout drawing terminal number ~ terminal name BD8108FM hsop-m28 fig.14 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 loadsw fail1 vreg pwm syn c gnd vda c ise t leden1 leden2 led1 led2 n.c. comp ss rt ovp en swout cs pgnd fail2 n.c. n.c. led4 led3 n.c. pin no. name of term inal function 1 vcc input power supply terminal 2 loadsw fet connection for load switch 3 fail1 output signal at abnormal time 4 vreg internal constant voltage output 5 pw m pw m light modulating input terminal 6 sync external synchronization signal input term inal 7 gnd gnd of small signal part 8 vdac dc variable light-modulating input term inal 9 iset led resistor for setting the output current 10 leden1 led output terminal enable terminal 1 11 leden2 led output terminal enable terminal 2 12 led1 led output terminal 13 - n.c. 14 led2 led output terminal 15 led3 led output terminal 16 - n.c 17 led4 led output terminal 18 - n.c. 19 - n.c. 20 fail2 led open/short detecting output signal 21 pgnd led output gnd terminal 22 cs dc/dc terminal for output current detecting 23 sw out dc/dc switching output terminal 24 en enable terminal 25 ovp overvoltage detecting terminal comp err amp vreg vcc en rt ovp osc ss control logic uvlo tsd ovp soft start pwm led1 led2 led3 current driver iset pgnd driver pwm comp swout ocp cs fail1 loadsw vreg sync vdac gnd open-short detect iset led4 leden1 leden2 fail2 4 2 1 24 6 26 28 27 5 8 9 10 11 20 21 17 15 14 12 7 22 23 3 25
5/16 5v constant voltage vreg 5v (typ.) is generated from vcc input voltage when en=h. this voltage is used as a power supply of the internal circuit, and also when the device pins need to be fixed to h voltage. uvlo is built-in in vreg, and the circuit begins to operat e when the voltage is more than 2.9v (typ.) and stops when the voltage is less than 2.8v (typ.). please connect creg=10uf (typ.) to vreg terminal for phase compensation. the circuit?s operation becomes remarkably unstable when creg is not connected. self-diagnosis function the operating condition of the built-in pr otection circuit is transmitted to fa il1 and fail2 output pins (open drain). when uvlo, ovp, ocp or tsd is operated, fail1 output becomes l swout is fixed to l, and the step-up conversion is stopped. for ocp, swout is fixed to l for only 1 cycle of fosc because of the pulse-to-pulse mode operation. for uvlo, ovp, tsd operations, led output pins become open (hi-z . when fail1 becomes l, loadsw is turned off as they are inverted to each other. fail2 output becomes l when open or short is detected. the open/short detection is a latch mode, and the latch is released by on/off (uvlo) of en. the device judges as open when led outpu t is lower than 0.15v (typ.) as well as when the voltage of ovp terminal reaches 1.7v (typ.). the short is detected when le d output becomes more than 4.5v (typ.). therefore, there is a possible scenario that short detection can not be carried out if the difference between led terminal voltage at the time of being normal and led terminal voltage at the time of being ab normal is less than 3.7v (4.5v-0.8v) (typ.). as for short detection hereon, if one led in some column of led output, for example, becomes short mode, and is in the status of nothing but vf being low, then cathode voltage is in the status of nothing but vf bei ng high. led short detection and ocp are separate protection circuits. please take care because short detec tion is masked as soon as open/short is detected. however, the open detection operates. an additional capacitance added to led output slows down the operation and the short may be detected. for the two fail output pins, add pull-up re sistors for each as they are open drain. constant-current driver please turn off the output with le den if there is constant -current driver output t hat is not used. the tr uth-table is shown bel ow. if constant-current driver output that is not used is not treated wi th leden but is made open, then the open detection will operate. also, please do not short the driv er output to gnd as the inputs of the e rror amplifier cannot be deactivated with leden. instead keep the driver output to open or short it to vreg. led en led a 1 ? a 2 ? 1 2 3 4 l l on on on on h l on on on off l h on on off off h h on off off off ovp ocp tsd uvlo fail1 open short fail2 s q r en=off (uvlo) mask led1 0.15v gnd 0.8v other led output 4.5v 0.8v step-up voltage vout vfxn+0.8v ovp 1.7v 2.0v led1 open led1 off short detection is not turned of f because it is masked. fail2
6/16 ~ setting method of output current iled=min[vdac , viset(=2.0v)] / rset x 3300 [ma] min[vdac , 2.0v] means the selection of sma ller value is between vdac or viset(=2.0v). 3300 (typ.) is a constant number determined by the circuit inside. when the output current needs to be controlled wi th vdac, please input in the range of 0.1 ? 2.0v. in the case of more than 2.0v, the value of viset is selected in such a way that it is given by the above-ment ioned calculating formula. please connect vdac with vreg if vdac is not to be used. the open state of vdac will cause malfunction. please do not change the led en status during the pwm operation. the following diagram shows the relation between riset and iset. for the intensity control with pwm, the on/off of current dr iver is controlled by pwm terminal. the duty ratio of pwm terminal becomes the duty ratio of iled. please fix the pwm termi nal to h if pwm intensity cont rol is not to be used (100%). it becomes brightest at the time of 100%. it is recommended to use a low-pass filter (cut off frequenc y: 30 khz) for the pwm pin. step-up dc/dc controller ~ number of leds in series connection output voltage of the step-up converter is controlled such that the led out put pin becomes 0.8v (typ.). step-up operation is performed only when led output is operating. when more t han one led outputs are operating, the led output in the column in which the led?s vf is the highest is controlled in such a way that it becomes 0.8v (typ.). the voltage of other led outputs are increas ed with the portion of variation becomes high voltage. please use the following equation to calculate allowable vf variation. vf variation allowable voltage 3.7v typ. = short detecting voltage 4.5v typ. led control voltage 0.8v typ. in addition, pay attention to the number of led?s connection in series because it has the following limits. in case of the open detection, 85% of ovp setting voltage becomes trigger, so the maximum value of step-up voltage under normal operation becomes 30.6v=36v x 0.85 and 30.6v / vf > maximum n number. ~ overvoltage protection circuit ovp for the ovp terminal, apply the voltage divider of the step-up converter output. t he setting value of ovp is determined by led?s total numbers in series connection and vf variation. pl ease also take ovpx0.85, which is the open detection trigger, into consideration when determining ovp setting voltage. once the ovp operates, the ovp is re leased when step-up voltage drops to 77.5% of ovp setting voltage. suppose rovp1 step-up voltage side ,rovp2 gnd side and step-up voltage vout, then vout>=(rovp1+rovp2)/rovp2 x 2.0v. the ovp operates at the time of rovp1=330k ? , rovp2=22k ? and vout= over 32v. pwm iled pwm iled(50ma/div) pwm iled pwm=150hz duty=50% pwm=150hz duty=0.38% pwm=20khz duty=50% *-&% wt3 4 &5 34&5<l
> *- & % <n " > *-&%?<n "> 34&5y iled actual measurement [ma] ------2.0/r setx3300
7/16 ~ oscillating frequenc y fos of step-up dc/dc converter triangular wave oscillating frequency can be set by connecting a resistor to rt (26pin). rt determines the charging & dischargi ng currents for internal condenser, and the frequency changes. please refer to the following theoretical formula when setting the rt?s resi stance. the range of 62.6k ? ? 523k ? is recommended. the setting that deviates from the fr equency range in the following diagram may cause the switching to stop and has no guarantee of pr oper operation, so please be careful. 3010 6 [v/a/s] is a constant number 16.6% determined by the circuit inside, and is the correction factor. rt : = 50k ? : 0.98 , 60 k ? : 0.985, 70 k ? : 0.99, 80 k ? : 0.994, 90 k ? : 0.996, 100k ? : 1.0, 150k ? : 1.01, 200k ? : 1.02,300k ? : 1.03 , 400k ? : 1.04 , 500k ? : 1.045 fosc = x [khz] fig.15 rt versus switching frequency ~ external synchronization oscillating frequency fsync please do not switch over to the internal oscillation etc. halfw ay when clock is being inputted to sync terminal for the purpos e of external synchronization for step-up dc/dc converter. from having switched the sync terminal from h to l till the internal oscillating circuit begins to operate, there is a delay time of about 30usec typ. . for the clock inputted to sync terminal, only the rising edge is effective. moreover, if external input fr equency is later than internal oscillating frequency, the internal oscillating circuit begins to operate af ter the above-mentioned delay time, so pl ease do not input something like that (the above-mentioned input). ~ overcurrent protection circuit ocp please put (insert) t he detecting resistor r cs between gnd and the source of n-mosfet for step-up dc/dc converter. in addition, please insert the lo w pass filter (lpf) with 1 ? 2mhz cutoff frequency between the cs terminal and the detecting resistor in order to reduce the switching no ise. if the time constant is too large, then the rising edge of cs terminal voltage is delayed, and it gets late t hat ocp operates. (rlpf=100 ? and clpf=1000pf etc. are effective at the time of fosc=300khz.) the detecting current is as follows. iocp=volimit0.4v / rcs [a] ocp is of pulse by pulse mode, and swout is fixed to l for onl y 1 cycle determined by fosc. in addition, there is a large current line between r cs gnd, so please pay special attention and make an independent wiring to gnd while board designing. ~ soft start ss for this ic, the ss terminal is not used, so please use the ic with the ss terminal open. moreover, the open/short detecting function is masked unt il ss terminal voltage reaches the vss clamp voltage 2.5v typ. . 30 10 6 rt [
] swo ut cs r cs lpf independent wiring to gnd vout (ac) il (500ma) sw , , , , , , 35<l
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:<l) [> fig.16 ripple current & voltage fre q uenc y
8/16 v out i out vcc v out -vcc vcc l v out f ? i l = [a] ~~~ 1 (v out - v cc) v out v out i rms = i out [a ] ~~ ~ 5 v out = i lmax r esr + [v] ~~~ 4 ? i l 2 v out i out vcc icc ? i l 2 i lmax = icc + = + [a] ~~~ 3 ? selection of external parts 1. selection of coil (l) the coil?s value greatly affects the input ripple current. as shown in formula (1), the ripple current decreases as the coil be comes larger or the switching frequency increases. when efficiency is represented as in (2), t he input peak current is as shown in (3). = ~~~ (2) t if current which exceeds the coil?s rated current value is r un through the coil, the coil caus es magnetic saturation and effici ency decreases. please keep a suitable margin so that the peak current does not exceed the coil?s rat ed current value, when selecting the curre nt. t please select coil with low resistance components (dcr and a cr) in order to minimize loss and improve efficiency. 2. setup of output condenser (co) the output condenser should be decided on after careful consideration of the stable zone of the output voltage and the necessary equivalent series resistance to smooth the ripple voltage. the output ripple voltage is decided as shown in formula (4). ( ? i l : output ripple current, esr: equival ent series resistance of co, : efficiency) t when selecting the condenser rating, keep a suitable margin for the output voltage. 3. selection of input condenser (cin) it is necessary to select a low-esr input condenser that can adequately deal with large ripple currents in order to prevent excess voltage. the ripple current i rms is derived from formula (5). also, because it depends greatly on the characteristics of the power supply used for input, the wiring pattern of the substrate and the mosfet gate-drain capacity, it is highly recommended that usage temperature, load range and mosfet conditions are adequately confirmed. i l i l v out l v cc i l c o fig.17 output ripple current i c o i out 1 f v out l v cc i l c o esr fig.18 output condenser v cc cin v out l i l c o i cc i lmax fig.19 input condenser
9/16 4. about mosfet for load switch and the corresponding soft start with regular booster applications, because no switch exists on the route from vcc to vo, t here is the threat of output short-circuit or destruction of the commutation diode. to avoid this, please insert a pmosfet load switch between vcc and the coil. pmosfet that can withstand higher pressure than vcc between both the gate sources and drain sources should be selected. also, if a load switch soft start is desired, please insert ca pacity between the gate source. refer to figure 21 when deciding on the soft start time. however, the soft start time changes depending on the gate capacity of pmosfet. fig.20 load switch circuit diagram fig.21 pg capacity vs. soft start time 5. selection of switching mosfet although there is no problem as long as the absolute maximum rating is the rated current of l and at least c?s pressure capacity and commutation diode?s vf, to actualize high-speed sw itching, one with small gate capacity (injected charge amount) should be selected. t excess current protection set up value or higher recommended. t high efficiency can be achieved if one with low on resistance is selected. 6. selection of commutation diode please select a schottky barrier diode with greater current capa bility than l?s rated current and reverse-pressure capacity greater than c?s pressure capacity, especially with low forward voltage vf. pg pin capacitor vs. soft start time 1.00e-05 1.00e-04 1.00e-03 1.00e-02 1.00e-01 1.00e-10 1.00e-09 1.00e-08 1.00e-07 1.00e-06 cpg [f] time [sec] delay [sec] risetime [sec] fet for load switch fet for switching l sbdi vo c t.b.d.
10/16 1 2 y lc o fr = [hz] 1 2 y lc o fr = [hz] resonance point phase-lag -180o at fig.22 fig.23 f esr = [hz] 1 2 r esr c o phase-lag -90 ? ? phase compensation setup rules ~ stability conditions of applications the stability conditions related to negative feedback are as follows: ~ when the gain is 1 (0db) and the phas e-lag is under 150 o (therefore wi th a phase margin of over 30o) also, a dc/dc converter application samples the switching frequency, so the gbw of the entire series is set to 1/10 below the s witching frequency. to summarize, the characteristi cs targeted by the application are as below: ~ when the gain is 1 (0db) and the phas e-lag is under 150 o (therefore with a phase margin of over 30 o) ~ gbw (frequency at gain 0db) at that time is 1/10 below the switching frequency therefore, to improve response with gbw limits, the switching frequency must be higher. a trick to secure stability with phase compensation is to cancel the second phase-lag (-180 o ) caused by the lc resonance with the second phase-lead (put in two phase-leads). phase-lead is by the esr component of the output condenser and t he cr of the error amp output comp terminal. with a dc/dc converter application, because t here is always an lc resonance circuit at the output, the phase- lag at that area i s -180o. when the output condenser is one with a large esr (several
), such as a aluminum electrolysis condenser, there is a phase-lead of +90o, and the phase-lag is -90o. when an output condenser with low esr such as a ceramic condenser is used, an r for the esr component should be inserted. lc resonance with esr because of the changes in phase characteristics caused by esr, one lead-phase should be inserted. fig.24 phase-lead fz = [hz] to setup the frequency to insert the phase-lead, for the aim of c anceling the lc resonance, ideally it should be set in the are a of the lc resonance frequency. because this setup was very basically design ed and strict calculations have not been made, adjustments with the actual equipment may be re quired. also, these characteristics change depending on factors such as different substr ate layouts and load cond itions, therefore when designing for mass production, adequate confirmati ons with actual equipment must be made. 1 2 cpcrpc vcc v o c o vcc v o c o r esr fb a comp v o rpc led cpc resonance point at phase-lead at
11/16 ? sequence t fix leden1 and 2 before input. fig.25 vcc en vreg uvlo pwm ovp ocp(cs) tsd load sw fail1 ( &yufsobm1vmm6q ) 2.9v 2.0v 1.6v 0.4v 175 ? 150 ? vreg off when tsd on internal signal internal signal 2.9v 4.5v vdac sync t pwmon > 500[v/a ~ s] x creg [sec] t pwmon > t inon t inon t pwmon t pwmoff > t inoff ok to input en at v cc = 4.5v or greater 2.8v v cc >vreg
12/16 ? power dissipation calculation pd(n) = icc*vcc + ciss*vsw*fsw*vsw + rload*(iload)^2 + [vled*n+ ? vf*(n-1)]*iled icc: maximum circuit current vcc: supply power voltage ciss: external fet capacity vsw: sw gate voltage fsw: se frequency rload: load sw on resistance iload: load sw maximum input current vled: led control voltage n: led parallel numeral vf: led vf fluctuation iled: led output current ? sample calculation ? pd(4) = 10ma 30v + 500pf 5v 300khz 5v + 15
(10ma) 2 + [0.8v 4 + vf 3] 100ma if vf = 3.0v, pd(4) = 324mw + 1220mw = 1544mw fig.26 note 1: the value of power dissipation is when mount ed on 70mm x 70mm x 1.6mm glass epoxy substrate (1-layer platform/copper thickness 18 m) note 2: the value changes with the copper foil density of the platform. however, this value represents observed value, not guaranteed value. pd=2200mw (968mw): substrate copper foil density 3% pd=3200mw (1408mw): substrate copper foil density34% pd=3500mw (1540mw): substrate copper foil density 60% value within brackets represent power dissipation when ta=95 ? ? efficiency of switching power supply efficiency is represented in the following formula: the main causes for power dissipation of the switching regulator p d are as listed below, and efficiency can be improved by lessening these causes. ? main causes of dissipation ? 1) dissipation from on resistance of coil and fet: pd(i 2 r) 2) gate charge-discharge dissipation: pd(gate) 3) switch dissipation: pd(sw) 4) condenser?s esr dissipation: pd(esr) 5) ic?s operational current dissipation: pd(ic) 1) pd(i 2 r) = i out 2 (r coil r on ) (r coil [
]: coil resistance, r on [
]: on resistance of fet, i out [a]: output current) 2) pd(gate) = c sw f sw v sw (c sw [f]: gate capacity of fet, f sw [hz]: switching frequency, v sw [v]: gate drive voltage of fet) 4) pd(esr) = i rms 2 esr (i rms [a]: ripple current of condenser, esr[
]: equivalent series resistance) 5) pd(ic) = vin i cc (i cc [a] : circuit current) 1pxfs%j ttj qbuj po led fluctuation ? 1pxfs%j ttj qbuj po1 e<n 8 > * -&% n " * -&% n " * -&% n " = 100[%] = 100[%] = 100[%] v out i out vin iin p out pin p out p d (ic) + p d 3) pd(sw) = (c rss [f]: reciprocal transmission capacity of fet, i drive [a]: pea k v in 2 c rss i out f sw i drive "ncjfou5fnqfsbuvsf5b 1pxfs%jttjqbujpo1e<,> 1 0
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13/16 fig.27 the decoupling condensers cvcc and creg should be plac ed as close as possible to the ic pin. there is a possibility that a large curr ent is sent to csgnd and pgnd, so each sh ould be independently wired, and at the same time impedance should be lowered. take care that there is no noise riding on 8pin vdac, 9pin iset, 26pin rt and 28pin comp. 5pin pwm, 6pin sync and 12-17pin led1-4 a ll switch, therefore be careful that the periphery pattern is unaffected. the areas with thick lines should be laid out as short as possible with wide patterns. ? pcb board external parts list setting place value product name manufacturer rld1 5.1k ? mcr03series5101 rohm rld2 5.1k ? mcr03series5101 rohm rfl1 5.1k ? mcr03series5101 rohm rfl2 5.1k ? mcr03series5101 rohm rpc 820 ? mcr03series8200 rohm rt 100k ? mcr03series1003 rohm rovp1 330k ? mcr03series3303 rohm rovp2 22k ? mcr03series2202 rohm rcs 0.1 ? mcr10seriesr10 rohm rset 100k ? mcr03series1003 rohm cpc 2.2uf t.b.d. murata css - - - cvcc 10uf grm21bb31c106ke15 murata creg 10uf grm21bb31c106ke15 murata q1 - rss090p03fu6tb rohm q2 - sp8k22fu6tb rohm l1 47uh cdrh8d38np-470nc sumida d1 - rb160l-60te25 rohm cvout 220uf 25yk220m0611 rubycon rlpf 100
mcr03series1000 rohm clpf 1000pf t.b.d. murata cld2 1uf t.b.d. murata t the above values are fixed numbers for confirmed operation when vcc=12v, led 5-straight 4-parallel and iled=50ma. therefore, because the optimal value varies depending on fa ctors such as usage conditions, the fixed numbers should be decided on after careful assessment.
14/16 ? in/output equivalent circuits (ter minal names surrounded by parentheses) 2. loadsw, 3. fail1, 20. fail2 4. vreg 5. pwm, 6. sync, 10. leden1, 11. leden2 8. vdac 9. iset 12. led1, 14. led2, 15. led3, 17. led4 22. cs 23. swout 24. en 25. ovp 26. rt 27. ss 28. comp 13, 16, 18, 19 n.c. cl10v t the value are all typ. value. cl10v n.c. rt ss 100k 50 2k 500 vdac 500 10k iset 5k 1k led1 ? 4 vcc vreg 150k 746k 255k en 172k 135k 10k swout 100k cl10v cl10v cs 5p 100 5k cl10v vreg cl10v cl10v cl10v cl10v 10k 150k cl10v vreg comp 2k 2k vreg n.c. is o p en. cl10v 10v 5k ovp cl10v vcc 167 1k
15/16 z operation notes 1) absolute maximum ratings use of the ic in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in ic damage. assumptions should not be made regarding the state of the ic (s hort mode or open mode) when such damage is suffered. a physical safety measure such as a fuse should be implemented when use of the ic in a special mode where the absolute maximum ratings may be exc eeded is anticipated. 2) gnd potential ensure a minimum gnd pin potential in all operating conditions. 3) setting of heat use a thermal design that allows for a sufficient margin in li ght of the power dissipation (pd) in actual operating conditions. 4) pin short and mistake fitting use caution when orienting and positioning the ic for mounting on printed circuit boar ds. improper mounting may result in damag e to the ic. shorts between output pins or between output pins and the power supply and gnd pins caused by t he presence of a foreign object may result in damage to the ic. 5) actions in strong magnetic field use caution when using the ic in the presence of a strong m agnetic field as doing so may c ause the ic to malfunction. 6) testing on application boards when testing the ic on an application board, c onnecting a capacitor to a pin with low impedance subjects the ic to stress. alwa ys discharge capacitors after each process or step. ground the ic during asse mbly steps as an antistatic measure, and use similar caution wh en transporting or storing the ic. always turn the ic's power supply off before connecting it to or removing it from a jig or fixt ure during the inspection process. 7) ground wiring patterns when using both small signal and large current gnd patterns, it is recommended to isolate the two ground patterns, placing a si ngle ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large current s do not cause variations in the small signal ground voltage. be careful not to change the gnd wiring patterns of any external components. 8) regarding input pin of the ic this monolithic ic contains p+ isolation and p substrate layers between adjacent element s in order to keep them isolated. p/n j unctions are formed at the intersection of these p layers with the n layers of other elements to create a variety of parasitic elements. for example, when the resistors and transisto rs are connected to the pins as shown in fig. 41, a parasitic diode or a transisto r operates by inverting the pin voltage and gnd voltage. the formation of parasitic elements as a result of the relations hips of the potentials of different pins is an inevitable resul t of the ic's architecture. the operation of parasitic elements can cause inte rference with circuit operation as well as ic malfunction and d amage. for these reasons, it is necessary to use caution so that the ic is not used in a way that will trigger the operation of parasitic elemen ts such as by the application of voltages lower than the gnd (p substrate) voltage to input and output pins. example of a simple monolithic ic architecture 9) overcurrent protection circuits an overcurrent protection circui t designed according to the output current is in corporated for the prevention of ic damage that may result in the event of load shorting. this protection circuit is effective in preventing damage due to sudden and unexpected accidents. howev er, the ic should not be used in applications characterized by the continuous operation or tr ansitioning of the protection circuits. at th e time of thermal designing, keep in mind that the current capacity has negative characteristics to temperatures. 10) thermal shutdown circuit (tsd) this ic incorporates a built-in tsd circui t for the protection from thermal destructi on. the ic should be used within the speci fied power dissipation range. however, in the event that the ic continues to be operated in excess of its power dissipation limits, the at tendant rise in the chip's junction temperature tj will trigger the tsd circuit to turn off all output po wer elements. the circuit automatically re sets once the junction temperature tj drops. operation of the tsd circuit pr esumes that the ic's absolute maximum ratings have been exceeded. application designs should nev er make use of the tsd circuit. 11) testing on application boards at the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure to discharge electricity per process because it may load stresses to the ic. always turn the ic's power supply off before connecting it to o r removing it from a jig or fixture during the inspection process. ground the ic du ring assembly steps as an antistatic measure, and use similar c aution when transporting or storing the ic. (pin a) gnd n p n n p+ p+ resistor parasitic elements p ? ? ? ? parasitic elements ( pin b ) gnd c b e parasitic elements gnd ( pin a ) ? ? gnd n p n n p+ p+ parasitic elements p substrate ( pin b ) c b e transistor (npn) ? ? n gnd
16/16 z selecting a model name when ordering the contents described herein are correct as of october, 2005 the contents described herein are subject to change without notice. for updates of the latest information, please contact and confirm with rohm co.,ltd. any part of this application note must not be duplicated or copied without our permission. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. p lease pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams and information, described herein are intended only a s illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose o f the same, implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. the products described herein utilize silicon as the main material. the products described herein are not designed to be x ray proof. published by application engineering group

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